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? semiconductor components industries, llc, 2016 january, 2016 ? rev. 8 1 publication order number: ncp5181/d ncp5181 high voltage high and low side driver the ncp5181 is a high voltage power mosfet driver providing two outputs for direct drive of 2 n?channel power mosfet s arranged in a half?bridge (or any other high?side + low?side) configuration. it uses the bootstrap technique to insure a proper drive of the high?side power switch. the driver works with 2 independent inputs to accommodate any topology (including half?bridge, asymmetrical half?bridge, active clamp and full?bridge ). features ? high voltage range: up to 600 v ? dv/dt immunity 50 v/nsec ? gate drive supply range from 10 v to 20 v ? high and low drv outputs ? output source / sink current capability 1.4 a / 2.2 a ? 3.3 v and 5 v input logic compatible ? up to v cc swing on input pins ? matched propagation delays between both channels ? outputs in phase with the inputs ? independent logic inputs to accommodate all topologies ? under v cc lockout (uvlo) for both channels ? pin to pin compatible with ir2181(s) ? these are pb?free devices applications ? high power energy management ? half?bridge power converters ? any complementary drive converters (asymmetrical half?bridge, active clamp) ? full?bridge converters ? bridge inverters for ups systems pin assignment pin function in_hi logic input for high side driver output in phase in_lo logic input for low side driver output in phase gnd ground drv_lo low side gate drive output v cc low side and main power supply v boot bootstrap power supply drv_hi high side gate drive output bridge bootstrap return or high side floating supply return www. onsemi.com marking diagrams pdip?8 p suffix case 626 device package shipping ? ordering information ncp5181p, 5181 = specific device code a = assembly location l = wafer lot y, yy = year w, ww = work week g or = pb?free package ncp5181p awl yywwg soic?8 d suffix case 751 ncp5181pg pdip?8 (pb?free) 50 units/tube ncp5181dr2g soic?8 (pb?free) 2.500/tape & ree l ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d. in_hi in_lo gnd drv_lo v boot drv_hi bridge v cc 5181 alywx 1 8 1 8
ncp5181 www. onsemi.com 2 q1 q2 c5 c6 c4 c3 gnd gnd gnd sg3526 mc34025 tl594 gnd gnd out+ out? u2 r1 d3 gnd l1 d1 d2 t1 5 in_hi 1 in_lo 2 gnd 3 drv_lo 4 bridge 6 drv_hi 7 vboot 8 u1 ncp51xx c3 c1 d4 figure 1. typical application v bulk v cc v cc level shifter r s q pulse trigger gnd gnd gnd drv_hi gnd gnd uv detect uv detect delay gnd figure 2. detailed block diagram v cc in_lo in_hi v cc bridge drv_lo drv_lo vboot drv_hi v cc q
ncp5181 www. onsemi.com 3 maximum ratings rating symbol value unit main power supply voltage v cc ?0.3 to 20 v vhv: high voltage boot pin v boot ?1 to 620 v vhv: high voltage bridge pin v bridge ?1 to 600 v vhv: floating supply voltage v boot ? v bridge 0 to 20 v vhv: high side output voltage v drv_hi v bridge ?0.3 to v boot +0.3 v low side output voltage v drv_lo ?0.3 to v cc +0.3 v allowable output slew rate dv bridge /d t 50 v/ns inputs in_hi, in_lo v in_xx ?1.0 to v cc +0.3 v esd capability: human body model (all pins except pins 6?7?8) machine model (all pins except pins 6?7?8) 2.0 200 kv v latchup capability per jedec jesd78 power dissipation and thermal characteristics pdip8: thermal resistance, junction?to?air so?8: thermal resistance, junction?to?air r ja r ja 100 178 c/w maximum operating junction temperature t j_max +150 c stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected.
ncp5181 www. onsemi.com 4 electrical characteristics (v cc = v boot = 15 v, v gnd = v bridge , ?40 c < t a < 125 c, outputs loaded with 1 nf) rating symbol t a ?40 c to 125 c units output section min typ max output high short circuit pulsed current v drv = 0 v, pw 10 s, (note 1) i drvhigh ? 1.4 ? a output low short circuit pulsed current v drv = v cc , pw 10 s, (note 1) i drvlow ? 2.2 ? a output resistor (typical value @ 25 c only) source r oh ? 5 12 output resistor (typical value @ 25 c only) sink r ol ? 2 8 dynamic output section rating symbol min typ max units turn?on propagation delay (v bridge = 0 v) t on ? 100 170 ns turn?off propagation delay (v bridge = 0 v or 50 v) (note 2) t off ? 100 170 ns output voltage risetime (from 10% to 90% @ v cc = 15 v) with 1 nf load t r ? 40 60 ns output voltage falling edge (from 90% to 10% @ v cc = 15 v) with 1 nf load t f ? 20 40 ns propagation delay matching between the high side and the low side @ 25 c (note 3) t ? 20 35 ns minimum input pulse width that changes the output t pw ? ? 100 ns input section low level input voltage threshold v in ? ? 0.8 v input pulldown resistor (v in < 0.5 v) r in ? 200 ? k high level input voltage threshold v in 2.3 ? ? v supply section v cc uv startup voltage threshold v cc_stup 7.9 8.9 9.8 v v cc uv shutdown voltage threshold v cc_shtdwn 7.3 8.2 9.0 v hysteresis on v cc v cc_hyst 0.3 0.7 ? v v boot startup voltage threshold reference to bridge pin (v boot_stup = v boot ? v bridge ) v boot_stup 7.9 8.9 9.8 v v boot uv shutdown voltage threshold v boot_shtdwn 7.3 8.2 9.0 v hysteresis on v boot v boot_shtdwn 0.3 0.7 ? v leakage current on high voltage pins to gnd (v boot = v bridge = drv_hi = 600 v) i hv_leak ? 0.5 40 a consumption in active mode (v cc = v boot , f sw = 100 khz and 1 nf load on both driver outputs) i cc1 ? 4.5 6.5 ma consumption in inhibition mode (v cc = v boot ) i cc2 ? 250 400 a v cc current consumption in inhibition mode i cc3 ? 215 ? a v boot current consumption in inhibition mode i cc4 ? 35 ? a *note: see also characterization curves 1. guaranteed by design. 2. turn?off propagation delay @ v bridge = 600 v is guaranteed by design 3. see characterization curve for t parameters variation on the full range temperature. 4. timing diagram definition see figures 4, 5 and 6.
ncp5181 www. onsemi.com 5 in_hi in_lo drv_hi drv_lo in_hi 50% 90% 90% 10% 10% in_lo drv_hi drv_lo 50% figure 3. input/output timing diagram figure 4. switching time waveform definitions 50% 90% 10% 50% 90% 10% drv_hi drv_lo in_lo in_hi delta_t delta_t figure 5. delay matching waveforms definition 50% 90% 10% 50% 90% 10% drv_hi drv_lo in_lo in_hi delta_t delta_t & figure 6. other delay matching waveforms definition t on t r t off t f t on t off t on t off t on_hi t on_lo t off_lo t off_hi
ncp5181 www. onsemi.com 6 typical characteristics figure 7. turn?on propagation delay vs. temperature figure 8. turn?on propagation delay vs. v cc voltage (v cc = v boot ) temperature ( c) supply voltage; v cc = v boot (v) 100 80 60 40 20 0 ?20 ?40 0 20 40 60 80 100 120 160 20 18 16 14 12 10 0 20 40 60 80 100 120 140 figure 9. turn?off propagation delay vs. temperature figure 10. turn?off propagation delay vs. v cc voltage (v cc = v boot ) temperature ( c) supply voltage; v cc = v boot (v) 100 80 60 40 20 0 ?20 ?40 0 20 40 60 80 100 160 180 20 18 16 14 12 10 0 20 40 60 80 100 120 160 figure 11. high side turn?on propagation delay vs. v bridge voltage figure 12. high side turn?off propagation delay vs. v bridge voltage bridge pin voltage (v) bridge pin voltage (v) 50 40 30 20 10 0 50 70 90 110 130 50 40 30 20 10 0 50 70 90 110 130 120 140 t on propagation delay (ns) t on propagation delay (ns) 120 120 140 t off propagation delay (ns) t off propagation delay (ns) t on propagation delay (ns) t off propagation delay (ns) 140 t on low side t on high side t on low side t on high side t off low side t off high side t off low side t off high side
ncp5181 www. onsemi.com 7 typical characteristics figure 13. turn?on rise time vs. temperature figure 14. turn?on rise time vs. v cc voltage (v cc = v boot ) temperature ( c) supply voltage; v cc = v boot (v) 100 80 60 40 20 0 ?20 ?40 0 5.0 10 15 20 25 30 40 20 18 16 14 12 10 0 5.0 10 15 20 25 30 35 figure 15. turn?off fall time vs. temperature figure 16. turn?off fall time vs. v cc voltage (v cc = v boot ) temperature ( c) supply voltage; v cc = v boot (v) 100 80 60 40 20 0 ?20 ?40 0 5.0 10 15 20 25 30 20 18 16 14 12 10 0 2.0 4.0 6.0 8.0 10 12 20 figure 17. propagation delay matching between high side and low side driver 120 35 turn?on rise time (ns) turn?on rise time (ns) 120 turn?off fall time (ns) turn?off fall time (ns) 14 16 18 t r low side t r high side t r low side t r high side t f low side t f high side t f low side t f high side temperature ( c) 100 80 60 40 20 0 ?20 ?40 0 5 10 15 20 25 30 40 120 35 propagation delay matching (ns)
ncp5181 www. onsemi.com 8 typical characteristics figure 18. low level input voltage threshold vs. temperature figure 19. low level input voltage threshold vs. v cc voltage temperature ( c) supply voltage; v cc = v boot (v) 0 0.2 0.6 1.0 1.4 20 18 16 14 12 10 0 0.2 0.4 1.0 1.4 low level input voltage threshold (v) low level input voltage threshold (v) 100 80 60 40 20 0 ?20 ?40 120 0.4 0.8 1.2 0.6 0.8 1.2 figure 20. high level input voltage threshold vs. temperature figure 21. high level input voltage threshold vs. v cc voltage temperature ( c) supply voltage; v cc = v boot (v) 100 80 60 40 20 0 ?20 ?40 0 0.5 1.0 1.5 2.5 20 18 16 14 12 10 0 0.5 1.0 1.5 2.0 2.5 figure 22. leakage current on high voltage pins (600 v) to ground vs. temperature figure 23. leakage current on high voltage pins to ground vs. v bridge voltage (v bridge = v boot = v drv_hi ) temperature ( c) bridge pin voltage (v) 100 80 60 40 20 0 ?20 ?40 0 0.5 1.0 1.5 2.5 3.0 4.0 600 400 300 200 100 0 0 0.05 0.10 0.15 0.20 0.25 0.40 120 2.0 120 leakage current to gnd ( a) high side leakage current to gnd ( a) 0.30 0.35 high level input voltage threshold (v) high level input voltage threshold (v) 2.0 3.5 500
ncp5181 www. onsemi.com 9 typical characteristics figure 24. high side supply current vs. temperature figure 25. high side supply current vs. bootstrap supply voltage temperature ( c) bootstrap supply voltage (v) 0 40 100 2 0 18 16 14 12 10 0 20 100 bootstrap supply current ( a) bootstrap supply current ( a) 100 80 60 40 20 0 ?20 ?40 120 20 60 80 40 60 80 figure 26. v cc supply current vs. temperature figure 27. v cc supply current vs. v cc supply voltage temperature ( c) v cc , supply voltage (v) 100 80 60 40 20 0 ?20 ?40 0 100 200 300 400 500 2 0 18 16 14 12 10 0 100 200 300 400 500 figure 28. uvlo start up voltage vs. temperature figure 29. uvlo shut down voltage vs. bootstrap supply voltage temperature ( c) temperature ( c) 100 80 60 40 20 0 ?20 ?40 8.0 8.2 8.6 8.8 9.0 9.8 10 120 80 20 0 ?20 ?40 7.0 7.2 7.4 7.6 7.8 8.0 8.2 9.0 120 v cc supply current ( a) v cc supply current ( a) 120 uvlo startup voltage th (v) uvlo shutdown voltage th (v) 8.4 8.6 8.8 8.4 9.2 9.4 9.6 40 60 100 v cc uvlo stup th v boot uvlo stup th v cc uvlo shtdwn th v boot uvlo shtdwn th
ncp5181 www. onsemi.com 10 typical characteristics figure 30. icc1 consumption vs. switching frequency with 15 nc load on each driver figure 31. icc1 consumption vs. switching frequency with 33 nc load on each driver switching frequency (khz) switching frequency (khz) 0 5.0 15 25 35 600 500 300 200 100 0 0 10 20 40 60 i cc + i boot current supply (ma) i cc + i boot current supply (ma) 500 400 300 200 100 0 600 10 20 30 30 50 400 r gate = 0 r gate = 10 r gate = 22 c load = 1 nf / q = 15 nc c load = 2.2 nf / q = 33 nc r gate = 0 r gate = 10 r gate = 22 figure 32. icc1 consumption vs. switching frequency with 50 nc load on each driver figure 33. icc1 consumption vs. switching frequency with 100 nc load on each driver switching frequency (khz) switching frequency (khz) 500 400 300 200 100 0 0 10 20 30 40 50 60 80 500 400 300 200 100 0 0 20 40 60 80 100 120 140 600 70 i cc + i boot current supply (ma) i cc + i boot current supply (ma) 600 r gate = 0 r gate = 10 r gate = 22 c load = 3.3 nf / q = 50 nc c load = 6.6 nf / q = 100 nc r gate = 0 r gate = 10 r gate = 22
ncp5181 www. onsemi.com 11 package dimensions 8 lead pdip case 626?05 issue p 14 5 8 b2 note 8 d b l a1 a eb e a top view c seating plane 0.010 ca side view end view end view with leads constrained dim min max inches a ???? 0.210 a1 0.015 ???? b 0.014 0.022 c 0.008 0.014 d 0.355 0.400 d1 0.005 ???? e 0.100 bsc e 0.300 0.325 m ???? 10 ??? 5.33 0.38 ??? 0.35 0.56 0.20 0.36 9.02 10.16 0.13 ??? 2.54 bsc 7.62 8.26 ??? 10 min max millimeters notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: inches. 3. dimensions a, a1 and l are measured with the pack- age seated in jedec seating plane gauge gs?3. 4. dimensions d, d1 and e1 do not include mold flash or protrusions. mold flash or protrusions are not to exceed 0.10 inch. 5. dimension e is measured at a point 0.015 below datum plane h with the leads constrained perpendicular to datum c. 6. dimension eb is measured at the lead tips with the leads unconstrained. 7. datum plane h is coincident with the bottom of the leads, where the leads exit the body. 8. package contour is optional (rounded or square corners). e1 0.240 0.280 6.10 7.11 b2 eb ???? 0.430 ??? 10.92 0.060 typ 1.52 typ e1 m 8x c d1 b a2 0.115 0.195 2.92 4.95 l 0.115 0.150 2.92 3.81 h note 5 e e/2 a2 note 3 m b m note 6 m
ncp5181 www. onsemi.com 12 package dimensions soic?8 nb case 751?07 issue ak seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 6. 751?01 thru 751?06 are obsolete. new standard is 751?07. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 ?x? ?y? g m y m 0.25 (0.010) ?z? y m 0.25 (0.010) z s x s m 1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155 mm inches scale 6:1 *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* on semiconductor and the are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of pa tents, trademarks, copyrights, trade secret s, and other intellectual property. a listin g of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any product s herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any part icular purpose, nor does sci llc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typi cal? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating param eters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgic al implant into the body, or other applications intended to s upport or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer s hall indemnify and hold scillc and its officers , employees, subsidiaries, affiliates, and dist ributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufac ture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 ncp5181/d literature fulfillment : literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative

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